The present invention is directed to semiconductor dies and, more particularly, to a semiconductor die with a specific die pad layout.
Semiconductor dies are cut from a wafer and attached to a lead frame or substrate and then encapsulated with a plastic material to protect the die from being physically damaged. The die typically includes a plurality of electrodes or die bond pads on its “active” surface. These electrodes are connected to corresponding connection points (e.g., lead fingers) on the lead frame or substrate in order to connect the die electrodes to package pins, which are external connection points that facilitate connection of the die internal circuitry to external circuitry.
The packaged die may be provided in various package types, such as a thin shrink small outline package (TSSOP) or Dual Flat No-leads (DFN) to accommodate different user requirements. FIG. 1A shows a 5-pin TSSOP 10 comprising a package body 12 and leads or pins 14 that extend outwardly from the package body 12. FIG. 1B is a cross-sectional view of the TSSOP 10, where a semiconductor die 16 is attached to a flag area of a lead frame and electrically connected to inner portions of leads 14 with bond wires 18. FIG. 2A shows a DFN package 20 having a package body 22 and external connection points 24, which typically are flush with the package body 22. FIG. 2B is a cross-sectional view of the DFN package 20, where the semiconductor die 16 is attached to a flag area of a lead frame and electrically connected to leads with bond wires 26.
Due to various package types and the placement of the die in the package (e.g., on top or bottom of the lead frame), different die layouts are necessary to satisfy requirements for standardized pin assignments. For example, FIG. 3A is a bottom cross-sectional view of the TSSOP 10 that shows the bond wires 18 extending from the die bonding pads to the inner portions of the leads 14. In this case, the wires 18 traverse minimal distances and do not cross with any of the other wires 18. FIG. 3B is a top cross-sectional view of the DFN package 20. However, for this package type, the wires 26 must traverse longer distances, such as across the width of the die 16 like the wires going to pins 2 and 3. Further, some of the wires 26 also cross each other, such as the wires going to pins 1 and 6, and the wires going to pins 3 and 4. Having longer wires and crisscrossing wires can cause assembly risks, yield losses and reduce assembly process speed. However, it also is expensive to provide different versions of the same die, having different pad layouts, to accommodate the different package types.
It therefore would be desirable to have a semiconductor die with its die pads arranged such that the die could accommodate different packaging needs yet maintain the same pin assignments without increasing assembly risks.